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November 15, 2021 at 1:04 pm #71650
Hi Ray, Thanks for the response. My name is Peter, and I’m working with Dave on this issue.
Looking at the datasheet for the PCA9555, I see that VIH, input HIGH voltage for SDA/SCL pins > 0.7 * Vdd. (see attached screen capture)
For Vdd = 5.0V, 0.7*Vdd = 3.5V, which is higher than the 3.3V logic signals generated by the MCU.
I’m working on adding a FET based level shifter to this ckt and some local pull-ups to 5V on the slave-side to see if that doesn’t resolve things.