That’s a very good point, I haven’t thought about it — for the initial implementation I focused on getting the firmware compatible with OS, but I haven’t thought about making it more efficient for RPi. Right now the inner loop uses nonblocking socket, and repeatedly checks schedule data and so on. Although the GPIO pins are only read/write once every second, the busy poll of the loop is probably consuming the entire CPU. One solution is to add a short sleep at the end of the loop to give the CPU some spare time. A more ideal solution is probably to make the algorithm event driven or interrupt driven. I will do a few tests this weekend, in the meantime, feel free to experiment with it and post your findings. Thanks.