September 30, 2019 at 12:26 pm #62779
On the latch solenoid driver
The P-FET and N-FET are controlled by a voltage divider connecting to both gates. Will shoot-through occur when switching state?
e.g. P-FET is off and N-FET is on. We want to flip the state. So the top P-FET gate voltage drops from 24V to 12V while N-FET gate voltage drops from 12V to 0V.
But when the P-FET drops to about say 22V, i.e. over the threshold, the P-FET turns on. At the instant, the N-FET gate voltage is at about 11V which means it is still in on state.
Am I missing something?
RegardsSeptember 30, 2019 at 8:01 pm #62791
That’s a good question. When I designed the Latching circuit I did try to avoid shoot-through problem — because I want to use one GPIO pin for each half H-bridge, this is a bit tricky. There are two things I’ve done to address this: one is that the resistor values (a pair of 10K and a pair of 470K) are picked intentionally to minimize the overlap of the P-MOS and N-MOS turning on at the same time; the other is that there is a 1ohm current limiting resistor (on the schematic it shows as a 2.2 with 2.2 in parallel) — if there is a very brief moment of shoot-through, that current has to go through the 1ohm power resistor, so the current is limited. Both AO3400 and AO3407 can handle a fair amount (up to 25A) of impulse current, so the resistor is there to avoid damaging the mosfets. This is not an ideal solution of course, as the shoot-through still discharges the capacitor quickly reducing useful voltage, but it is an effective solution to avoid damaging the mosfets.
I’ve checked the circuit under oscilloscope, there is a brief moment (a couple microsecond) of shoot-through, mostly because when the boosted voltage comes in from BSTV line, there is a brief moment where the MOSFET dynamics causes them to deviate from idea behavior. I couldn’t figure out how to get rid of this. As I said, the 1ohm power resistor really helped here.
If there are enough GPIO pins, I would definitely use the standard design where each half H-bridge is controlled by two separate GPIO pins. But since ESP8266 has very limited number of GPIOs, I have to settle with the current solution.
By the way: to answer your question: when BSTV is 22V, the status of the two mosfets depends on the gate-controller mosfet QB. If QB is turned off, i.e. its drain to source is disconnected, then the P-MOS is off, N-MOS is on, because the entire 22V gets splits by two 10K and two 470K, since 470K is significantly higher than 10K, the voltage drop on the P-MOS is almost 0, so it cannot possibly turn on. At this moment, the N-MOS is on, so the output is grounded.
If QB is on, i.e. is drain is grounded, then 22V is split on the two 10K, which generates enough gate voltage on the P-MOS, so that P-MOS turns on; at the same time, the N-MOS’s gate is grounded, so that turns off, the end result is that the output is high (~22V).
If you look at the firmware code: it always configures QB before high voltage is sent to BSTV. So QB’s state is fully determined before high voltage is present on BSTV. It never changes the state of QB while BSTV is active. So the condition you mentioned that QB toggles states does not happen in the code.October 1, 2019 at 10:42 pm #62804
Thanks for your explanation.
You must be logged in to reply to this topic.